Clocking-related elements of an integrated circuit (IC) often consume a significant amount of power. Clocking-related elements may include circuits used for clock generation and clock distribution. Dual edge-triggered (DET) flip-flops have recently been employed to reduce the amount of power consumed by clocking-related elements. DET flip-flops are triggered on the rising edge and on the falling edge of a clock signal. A system using DET flip-flops may provide the same throughput as a single edge-triggered system while operating at half the clock frequency and consuming half the power of the single edge-triggered system.
IC power consumption may be further reduced using clock gating techniques. Clock gating generally consists of disabling the clock signal, and therefore the switching power, to an unused functional block of an IC. Clock gating is usually implemented by clock gating signals and clock gating cells. Conventional clock gating cells are unsatisfactory for use in conjunction with functional blocks employing DET flip-flops.